Conventional far back-end-of-line (FBEOL) processes for fabricating smaller scaled semiconductor devices (e.g., 32 nm and 22 nm) use aluminum pads that support a controlled collapse chip connection (C4) element and the corresponding underbump metallurgy (UBM). As dimensions of features (e.g., pads, wires, interconnects, vias, etc.) continue to shrink to create smaller devices, the maximum allowable current density decreases rapidly due to element electromigration (EM) effects. This crowding of current associated with the C4 and the aluminum pad and/or via structures often results in EM void formation, which can lead to increased resistance that negatively affects the performance of the semiconductor device.